Paper
Evaluation of Fibonacci Test Pattern Generator for Cost Effective IC Testing
- Authors:
- Tanveer Ahmed; Liakot Ali
- Abstract
- Integrated Circuits (ICs) are the key components in all modern electronic equipments. With the increase in complexities of ICs, it is a challenging issue to test ICs at low cost with reliable performance. In this paper we investigate the performance of IC. It is shown that Fibonacci Linear Feedback Shift Register (FLFSR) performs better in testing of IC. This paper presents a new architecture for test pattern generator that produces the highest fault coverage (FC) with minimum number of pseudo random test vectors. This paper focuses on the design and implementation of a 64-bit Fibonacci test pattern generator capable of generating sufficient long test pattern and conducting fault simulation experiments on International Symposium on Circuits and Systems (ISCAS) benchmark circuits. Test pattern generator is very important in VLSI Testing. By changing the seed and feedback connection, a set of test vectors was generated for different benchmark circuits. The objective was to produce Test Pattern with good randomness; then fault coverage will be better. Fault simulation was done using FSIM fault simulator.
- Keywords
- Linear Feedback Shift Register (LFSR); Fibonacci Linear Feedback Shift Register (FLFSR); Galois Linear Feedback Shift Register (GLFSR); Fault Coverage (FC); Test Vector (TV)
- StartPage
- 28
- EndPage
- 36
- Doi