Consumer Electronics Times                                  
Consumer Electronics Times(CET)
ISSN:2304-1846(Print)
ISSN:2304-1854(Online)
Frequency: Quarterly
Website: www.academicpub.org/cet/
Review of Reconfigurable Architectures for the Next Generation of Mobile Device Telecommunications Systems
Full Paper(PDF, 1661KB)
Abstract:
The development of mobile devices has challenged hardware designers to come up with suitable architectures. Challenges such as power consumption, flexibility, processing power and area are likely to lead to the need for a reconfigurable architecture to cater for the growing demands made of mobile devices, and to suit the needs of the next generation of devices. Parallelism and multifunction in real-time will be the minimum required characteristics of the architectures of such devices. This chapter reviews the currently available reconfigurable architectures. The focus here is on coarse-grain reconfigurable architectures, with particular attention to those which support dynamic reconfiguration with low-power consumption. The capacity for dynamic reconfiguration will be a key factor in defining the most suitable architecture for future generations of mobile devices. This paper describes existing reconfigurable platforms. Their principles of operation, architectures and structures are discussed highlighting their advantages and disadvantages. Various coarse-grain reconfigurable architectures are discussed along with their improvement with time. Finally, the key characteristics which are required for a reconfigurable architecture to be suitable for telecommunication systems are identified. A comparison is given for the various architectures discussed in terms of suitability for telecommunications applications.
Keywords:Coarse Grain Reconfigurable Architecture; FPGA; ASIC; DSP; Dynamic Reconfiguration; Low Power Consumption
Author: Ahmed O. El-Rayis1, Tughrul Arslan1, Khalid Benkrid1
1.School of Engineering, The University of Edinburgh, Edinburgh EH9 3JL, UK
References:
  1. G. Estrin, B. Bussel, R. Turn, and J. Bibb, “Parallel processing in a restructurable computer system,” IEEE Transactions on Electronic Computers, vol. EC-12, no. 6, pp. 747-755, Dec. 1963.
  2. W. Carter, K Duong, R H Freeman, H Hsieh, J Y Ja, J E Mahoney, L T Ngo, er al., “A user programmable reconfigurable gate array,” in Proc. CICC, pp. 233-235, May 1986.
  3. “FPGA - Field Programmable Gate Array,” available: http://www.fpgacentral.com/pld-types/fpga-field-programmable-gate-array, accessed on 11/9/2014.
  4. The Industry’s Breakthrough 7 Series FPGA Families, available at http://www.xilinx.com/products/silicon-devices/fpga/index.htm, accessed on 11/9/2014.
  5. R. D.Wittig and P. Chow, “One Chip: an FPGA processor with reconfigurable logic,” Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 126-135, Apr. 1996.
  6. R. Razdan, M. D. Smith, “A high-performance microarchitecture with hardware-programmable functional units,” Proceedings of the 27th Annual International Symposium on Microarchitecture, MICRO-27, pp. 172-180, 30 Nov-2 Dec. 1994.
  7. S. Hauck, T.W. Fry, M.M. Hosler, J. P. Kao, “The Chimaera reconfigurable functional unit,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 206-217, Feb. 2004.
  8. Takashi Miyamori and Kunle Olukotun, “REMARC: Reconfigurable Multimedia Array Coprocessor,” IEICE Transactions on Information and Systems E82-D, pp. 389-397, 1998.
  9. Carl Ebeling and DarrenC. Cronquist, and Paul Franklin, “RaPiD - Reconfigurable pipelined datapath,” Lecture Notes in Computer Science: Field-Programmable Logic Smart Applications, New Paradigms and Compilers, vol. 1142, pp. 126-135, 1996.
  10. Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad Hutchings, “A reconfigurable arithmetic array for multimedia applications,” Proceedings of ACM/SIGDA seventh international symposium on Field programmable gate arrays, pp. 135-143, 1999.
  11. J. Becker, T. Pionteck, C. Habermann, M. Glesner, “Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture,” IEEE Computer Society Workshop on VLSI, pp. 41-46, May 2001.
  12. Francisco Barat, Murali Jayapala, Tom Vander Aa, et al. edited by Cheung, George Constantinides, “Low Power Coarse-Grained Reconfigurable Instruction Set Processor,” In Field Programmable Logic and Application, vol. 2778, pp. 230-239, 2003.
  13. G. Sassatelli, G. Cambon, J. Galy, L. Torres, “A dynamically reconfigurable architecture for embedded systems,” 12th International Workshop on Rapid System Prototyping, pp. 32-37, 2001.
  14. E. Mirsky, A. DeHon, “MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources,” IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157-166, 17-19, Apr. 1996.
  15. Lisa J K Durbeck and Nicholas J Macias, “The Cell Matrix: an architecture for nanocomputing,” Nanotechnology Journal, vol. 12, no. 3, pp. 217-230, 2001.
  16. H. Zhang, V. Prabhu, V. George, M.Wan, M. Benes, A. Abnous, J.M. Rabaey, “A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications,” IEEE International Solid-State Circuits Conference, pp. 68-69, Feb. 2000.
  17. J. R. Hauser, J. Wawrzynek, “Garp: a MIPS processor with a reconfigurable coprocessor,” The 5th Annual IEEE Symposium Proceedings on Field-Programmable Custom Computing Machines, pp. 12-21, 16-18 Apr. 1997.
  18. Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna, “A Self-Reconfigurable Gate Array Architecture,” Proceedings of The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications, Springer-Verlag, pp. 106-120, 2000.
  19. R. David, D. Chillet, S. Pillement, O. Sentieys, “DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints,” Proceedings Parallel and Distributed Processing International Symposium, vol. 8, pp. 15-19, April 2001.
  20. D. C. Chen and J. M. Rabaey, “PADDI: Programmable Arithmatic Devices for Digital Signal Processing,” In VLSI Signal Processing IV, pp. 240-249, IEEE Press, Nov. 1990.
  21. D.C. Chen and J.M. Rabaey, “A Reconfigurable Multiprocessor IC for Rapid Prototyping of Real Time Data Paths,” IEEE Journal of Solid State Circuits, vol. 27, no. 12, pp. 1895-1992.
  22. P. Hilfinger, “A high-level language and silicon compiler for digital signal processing,” in proceedings IEEE Custom Integrated Circuits Conferences, pp. 240-243, May 1985.
  23. H. Singh, Lee Ming-Hau, Lu Guangming, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications,” IEEE Transactions on Computers, vol. 49, no. 5, pp. 465-481, May 2000.
  24. S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer, “PipeRench: a coprocessor for streaming multimedia acceleration,” Proceedings of the 26th International Symposium on Computer Architecture, pp. 28-39, 1999.
  25. R. Hartenstein, M. Herz, T. Hoffmann, U. Nageldinger, “On Reconfigurable Co-Processing Units,” Proceedings of Reconfigurable Architectures Workshop (RAW98), held in conjunction with 12th International Parallel Processing Symposium (IPPS-98) and 9th Symposium on Parallel and Distributed Processing (SPDP-98), Orlando, Florida, USA, March 30,1998.
  26. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, “Using the KressArray for reconfigurable computing,” Proceeding of SPIE, Configurable Computing: Technology and Applications, vol. 3526, Boston, USA, 1998.
  27. R. W. Hartenstein, R. Kress, “A datapath synthesis system for the reconfigurable datapath architecture,” Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal, pp. 479-484, 29 Aug-1 Sep 1995.
  28. H. Corporaal, “Design of transport triggered architectures,” Proceedings of Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, pp. 130-135, 4-5 Mar 1994.
  29. J. Heikkinen, J. Sertamo, T. Rautiainen, J.Takala, “Design of transport triggered architecture processor for discrete cosine transform,” 15th Annual IEEE International ASIC/SOC Conference, pp. 87-91, 25-28 Sept. 2002.
  30. P. Hamalainen,; J. Heikkinen, M. Hannikainen, T.D. Hamalainen, “Design of transport triggered architecture processors for wireless encryption,” 8th Euromicro Conference on Digital System Design Proceedings, pp. 144-152, 30 Aug.-3 Sept. 2005.
  31. J. Heikkinen, J. Takala, A. Cilio, and H. Corporaal, “On Efficiency of Transport Triggered Architectures in DSP Applications,” in Advances in Systems Engineering, Signal Processing and Communications, N. Mastorakis, Ed., pp. 25-29, WSES Press, New York, NY, USA, 2002.
  32. He Yifan, She Dongrui, B. Mesman, H. Corporaal, “MOVE-Pro: A low power and high code density TTA architecture,” International Conference on Embedded Computer Systems (SAMOS), pp. 294-301, 18-21 July 2011.
  33. S. Khawam, I. Nousias, M. Milward, Yi Ying, M. Muir, T. Arslan, “The Reconfigurable Instruction Cell Array,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 75-85, Jan. 2008.
  34. A. Major, Yi Ying, I. Nousias, M. Milward, S. Khawam, T. Arslan, “H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture,” IEEE International SOC Conference, pp. 49-52, 24-27 Sept. 2006.
  35. Z. Wang, A.T. Erdogan, T. Arslan, “A SDR Platform for Mobile Wi-Fi/3G UMTS System on a Dynamic Reconfigurable Architecture,” 2009 European Signal Processing Conference (EUSIPCO-2009), Glasgow, UK, August 24-28, 2009.
  36. I. Nousias, S. Khawam, M. Milward, M. Muir, T. Arslan, “A Multi-objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays,” the 17th International Conference on Field Programmable Logic and Applications (FPL 2007), pp. 497-500, Amsterdam, Netherlands, 27-29 August 2007.
  37. Z. Wang, T. Arslan, A.T. Erdogan, “Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture,” 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), pp. 148-152, 23-25 Jan. 2008.
  38. T. Hirao, Kim Dahoo, I. Hida, T. Asai, M. Motomura, “A restricted dynamically reconfigurable architecture for low power processors,” International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 1-7, Dec. 2013.
  39. O. Atak, A. Atalar, “BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no.7, pp. 1285-1298, July 2013.
  40. R.W. Brodersen, J.M. Rabaey, “Evolution of Microsystem Design,” Proceedings of the 15th European Solid-State Circuits Conference ESSCIRC '89, pp. 208-217, 20-22 Sept. 1989.
  41. R. Hartenstein, “Coarse grain reconfigurable architectures,” In Proceedings of the 2001 Asia and South Pacific Design Automation Conference (ASP-DAC '01). ACM, New York, USA, pp. 564-570, 2001.